1. Field of the Invention
The present invention relates to a wireless transceiver that transmits and receives a signal by wireless and a wireless transmission method.
2. Description of the Related Art
In recent years, wireless communication systems have dramatically progressed, and compact wireless transceivers capable of transmitting and receiving signals by wireless have been provided.
For example, Japanese Patent Application Laid-Open Publication No. 2005-20119 discloses a wireless communication system that has a direct-current (DC) offset canceling function and a gain adjusting function that are used in signal reception.
According to Japanese Patent Application Laid-Open Publication No. 2005-20119, DC offsets of the amplifier that amplifies the received signal are previously detected for various set gains to determine offset canceling values, the offset canceling values are stored in a memory, and an appropriate offset canceling value is read out from the memory to cancel the DC offset of the amplifier when signal reception is started or the gain is changed.
However, DC offset canceling is important not only in reception but also in transmission.
To precisely cancel or reduce the DC offset of a transmitting part, DC offsets of a plurality of circuit blocks (having different functions) in the transmitting part are desired to be canceled or reduced.
Furthermore, in IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, 2003, “A single-Chip Digitally Calibrated 5.15-5.825-GHz 0.18-μm CMOS Transceiver for 802.11a Wireless LAN”, a wireless transceiver 41 shown in FIG. 9 is disclosed.
The wireless transceiver 41 has a receiving part 2′ that receives a signal transmitted by wireless, a transmitting part 3′ that transmits a signal by wireless, and a digital controlling circuit (referred to simply as controlling circuit hereinafter) 4′ that controls the receiving part 2′ and the transmitting part 3′.
Furthermore, the wireless transceiver 41 has an antenna 5 at which a transmission signal produced by the transmitting part 3′ is externally transmitted via a radio wave and a radio wave externally transmitted is received, and a switch 6 that switchably connects the antenna 5 to the transmitting part 3′ or the receiving part 2′.
A signal received at the antenna 5 (RX in FIG. 9) is amplified by a low noise amplifier (abbreviated as LNA hereinafter) 11, and then input to a receiving mixer 12. The receiving mixer 12 also receives a local oscillation signal (not shown) and down-converts the received signal by mixing with the local oscillation signal. The signal down-converted by the receiving mixer 12 is input to a low pass filter (abbreviated as LPF hereinafter) 13. The LPF 13 extracts an intermediate frequency signal component in a lower frequency range.
The intermediate frequency signal is input to a variable gain amplifying circuit (referred to also as variable gain amplifier and abbreviated as VGA hereinafter) 15. The signal is amplified by the VGA 15, and then input to an analog-to-digital converting circuit (abbreviated as ADC hereinafter) 16 via a contact a of a switch 14.
The digital signal produced by analog-to-digital conversion in the ADC 16 is input to the controlling circuit 4′. The controlling circuit 4′ performs demodulation, compensation control or the like of the input signal and outputs the resulting signal to a subsequent stage (not shown).
In transmission, the controlling circuit 4′ outputs a digital signal, such as a digital modulation signal, to a digital-to-analog converting circuit (abbreviated as DAC hereinafter) 17 in the transmitting part 3′. The analog output signal of the DAC 17 produced by digital-to-analog conversion is output to an LPF 18 and to a contact d of the switch 14 via a monitoring signal line 19a. 
The LPF 18 removes an unwanted frequency component, and the original modulation signal components passes through the LPF 18 and is output to a transmitting mixer 21 and to a contact c of the switch 14 via a monitoring signal line 19b. 
The transmitting mixer 21 up-converts the signal input from the LPF 18, and then outputs the up-converted signal to a power amplifier (abbreviated as PA hereinafter) 22 and to a contact b of the switch 14 via a monitoring signal line 19c. The power of the signal is amplified by the PA 22, and the amplified signal is transmitted by radio from the antenna 5 as a transmission signal (TX in FIG. 9) via the switch 6.
A signal line extending from the LNA 11 to the ADC 16 in the receiving part 2′ described above is a differential signal line and actually is a pair of signal lines. Similarly, a signal line extending from an output terminal of the DAC 17 to an output terminal of the PA 22 and the monitoring signal lines 19a to 19c are differential signal lines, and each signal line is actually a pair of signal lines.
The controlling circuit 4′ has a parameter register 4a, for example, and supplies a parameter stored in the parameter register 4a to the DAC 17, the LPF 18 and the transmitting mixer 21 via parameter control lines 23a to 23c for compensating for a DC offset or the like.
In such an example of the conventional configuration, as a method of compensating for the DC offset of each circuit block forming the transmitting part 3′, a feedback control in which parameters are configured so that the output of the ADC 16 becomes a predetermined value (0 in this case) is performed. Alternatively, a look-up table (abbreviated as LUT, not shown) control in which information in an LUT is read out from the output of the ADC 16 and a corresponding parameter is set is also possible.
However, when the DC offset of each circuit block, such as DAC 17, forming the transmitting part 3′ is compensated for, the wireless transceiver 41 shown in FIG. 9 has a disadvantage described below because the output signals of the DAC 17 and the like are input to the ADC 16 via the monitoring signal lines 19a to 19c. 
For example, in a case where the ADC 16 is 6-bit, the DAC 17 is 10-bit, and the input to the ADC 16 is 1 V at the maximum, and the output of the DAC 17 is also 1 V at the maximum, the resolution of the ADC 16, 1 LSB, is about 16 mV.
In this case, even if the ADC 16 has no DC offset (or a DC offset equal to or lower than 1 LSB), 1 LSB of the DAC 17 is about 1 mV, and there arises a problem that, if a few bits of DC offset occurs in the output of the DAC 17, the DC offset cannot be detected.
Thus, a wireless transceiver capable of precisely canceling or reducing the DC offset of the transmitting part 3′ is required.
In this case, since the VGA 15 precedes the ADC 16, it is preferable that DC offset canceling or reduction be performed using the amplifying circuit, including the VGA 15, without using an additional circuit element.